Improving Productivity Using Formal Analysis by Designers

Formal analysis is a very powerful verification technique, but it has usually been regarded as a method to be used only by expert verification engineers. Recently, standard assertion formats, improved technology, and pragmatic methodologies have all contributed to make formal analysis very useful for designers as well. At multiple teams within STMicroelectronics, formal analysis with Incisive Formal Verifier (IFV) is becoming a mainstream approach for design and verification engineers alike. In this paper, we discuss several important aspects of deploying formal analysis throughout recent projects. We outline the verification flow prior to the introduction of formal, and describe the motivation to investigate this technology. We considered our initial usage quite successful: IFV found a previously unknown bug in a complex DRAM refresh controller and verified two additional blocks in only three days, versus three weeks for a similar block on a previous project. The largest section of this paper covers our most recent experience using IFV to verify a customer design. We describe how and why we selected particular blocks in this complex controller for formal analysis and why we decided against others. We discuss some of the assertions written by the designers, outline the challenges faced in properly constraining the design for formal, and give some examples of the types of design bugs we found. We also cover the role of assertions in system verification as well as some specific issues regarding gated clocks that we had to address. Finally, we summarize the overall verification results for this project and the lessons we learned for application on future projects. Throughout this paper, we focus on the designer’s role. Strong designer involvement has been a key for growth in the usage of formal analysis and we are pleased to be able to report our success in this area.